The design and development of an integrated circuit is an expensive and time-consuming process, during which many different activities, from product definition to design to layout verification and simulation are performed, all prior to fabrication of a prototype IC. To verify operability of a layout and permit optimizations or changes, and to reduce potential defects within an IC, after a layout is created a layout versus schematic (LVS) verification process may occur. Such a process is used to compare a layout version of the IC to a schematic version of the IC to determine correspondence between the two versions.
Software tools are available for LVS verification. These tools typically compare the connectivities of an IC layout with the connectivities of a schematic of the IC to verify a one-to-one correspondence. That is, an IC design may be represented by an electrical schematic containing devices and nets interconnecting the devices together, and by geometric layout data that describes patterns of regions or elements to be formed in and/or on an integrated circuit substrate (e.g., a wafer).
Tools to perform layout versus schematic comparisons may include extraction software to extract a layout netlist from geometric layout data. The extracted layout netlist can then be compared to an electrical schematic netlist to determine functional equivalence between the schematic and the layout.
In an analog IC, a layout typically includes a number of different cells, each having different functionalities. Furthermore, various cells may operate using different supply voltages. In other words, the different cells operate at different supply voltage domains. Inherent in the provision of different supply voltages is the risk of shorting two or more of the supplies together.
To provide protection between different cells operating at different supply domains, analog ICs often include different regions to isolate one cell (and accordingly one supply voltage domain) from another. Furthermore, the operation of an analog IC may produce electrical activity that spans a wide frequency spectrum, including the radio frequency (RF) range, which has a tendency to generate a significant level of substrate current if no measures are taken to limit this current.
Thus for these reasons, active devices within an analog IC design are typically formed inside protected regions of a substrate on which the IC is formed. For example, an n donor-type region (called a “deep n-well”) of a p donor-type substrate can provide a degree of isolation between the devices and the substrate, and maintain isolation between cells operating at different voltages. Other well regions can also be present in a design, such as n-wells that form a ring around one or more cells operating at a given supply voltage.
When modeling these well regions of an IC during a LVS verification process, it is possible for short circuits isolated by these regions, among other such structures, to not be detected. If these short circuits are not detected during the LVS process, a design flaw causing the short circuit can remain in the layout. Thus when prototype ICs are fabricated, they will have the short circuit causing additional expense and delay in debugging and correcting the short circuit.
A need thus exists to more effectively verify an IC design.